A component under test is typically a simulated component that has test scenarios applied thereto to verify whether the component is behaving as expected. The test scenarios are selected to stress the component to ensure that the component when stressed still acts appropriately. For example, if the component under test is a unit of memory, then test scenarios are applied against the unit of memory to verify that the data ultimately stored in the memory is the correct data.
One test scenario that is typically applied to a component under test is a scenario that causes stressful address conflicts. Addresses are provided to requestors and those requestors target the component under test using the provided addresses. The goal is to stress the component under test to verify how well the component responds.
The success of the test, however, depends on the addresses that are provided to the requesters. Previously, techniques have been employed to generate and select addresses to be used by the requesters. However, the generation and selection techniques have heretofore been disjoint causing the selection of addresses that did not meet the needs of the requesters. For example, stressful address conflicts were unable to be created or were difficult to create.
Thus, a need exists for an enhanced capability to generate and select addresses to be used in a verification environment. For example, a need exists for a capability that tightly couples the generation and selection of addresses.